Increased variations in the electrical characteristics of complementary-metal-oxide semiconductor (CMOS) devices and process structures with scaling of device geometries produces fewer functional components and amongst components that function, fewer components that meet specifications for performance and leakage power. This increase in the electrical variability of CMOS devices and process structures can be controlled to a certain extent by iteratively refining the CMOS process integration to enable device parameters and their spreads to be centered precisely at regions that maximize satisfaction of yield, performance and leakage targets. The device parameter spreads induced by the intrinsic device variability can be minimized through the selection and optimization of device design attributes such as the distribution and concentration of dopant impurity atoms in the devices.
Iterative refining of the CMOS process requires a fast feedback between statistical characterization of device and process structures and a revised process integration sequence where implant energy, dose of small geometry yield detracting bitcell transistors for example, are incrementally adjusted to enable the process of the technology being developed to reach its targets. Traditional structures that provided this feedback on the chip kerf were built based on an outdated manufacturing paradigm from over 20 years ago that implicitly assumes an absence of random local variability and an absence of as large an impact of manufacturing variations (e.g., optical aberrations, variations in exposure, mask geometries, materials used, uniformity of resist thickness across wafer/lot, etc.) on electrical characteristics of small geometry structures.
Therefore, updated and improved techniques for statistical characterization of process and device structures are needed for process integration teams to rapidly assess both the mean values of electrical characteristics of devices and also their statistical spreads. ‘Flycell’-type macros on the kerf that typically include a few to a few dozen structures for characterization do not provide adequate statistics for characterization since the “statistical confidence” of the sample size they offer are insufficient to accurately estimate the mean or the actual spreads of component characteristics in actual products. It is inefficient and expensive to dedicate additional non-product chip area to provide a greater quantity of “Flycell” test structures to improve the statistical confidence in the characterization of the device spreads.
Given structures on the kerf that are repeated at least a few thousand times (minimum to enable a hardware-based three sigma statistical characterization), the time consumed in characterizing the electrical characteristics during technology development can be very significant for a wafer start given the large number of such structures (e.g., several dozen process structures, several dozen device structures and several dozen circuit structures) and each of their individual sample sizes. Measurement times using standard parametric testers (again a product of an outdated manufacturing paradigm from over 20 years ago) inline (between manufacturing steps) can consume several hundred milliseconds to over a second for each unique measurement.
Thus, for example, getting a single DC measurement from 1,000 samples per chip for each of 100 (process, device and circuit) structures can take as long as 1,000 samples×100 structures×700 milliseconds (ms) or 20 hours for a single chip. Multiplying this number by 40 chips per wafer and 12 wafers per lot results in an overhead of 400 days for a single lot, which is unacceptable.
In addition, the number of test pad structures in the conventional characterization follows the number of devices, or samples. Therefore, the total chip area consumed by the conventional test structure will be proportional to the number of devices tested, and becomes unworkable in the case of, e.g., 1,000 samples per chip. Clearly, the economics do not permit manufacturing semiconductor components using paradigms that are carried over from the past.